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DS1286 watchdog timekeeper DS1286 022798 1/12 features ? keeps track of hundredths of seconds, seconds, min- utes, hours, days, date of the month, months, and years; valid leap year compensation up to 2100 ? watchdog timer restarts an outofcontrol processor ? alarm function schedules real timerelated activities ? embedded lithium energy cell maintains time, watch- dog, user ram, and alarm information ? programmable interrupts and square wave outputs maintain 28pin jedec footprint ? all registers are individually addressable via the ad- dress and data bus ? accuracy is better than 1 minute/month at 25 c ? greater than 10 years of timekeeping in the absence of v cc ? 50 bytes of user nv ram pin assignment v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 nc nc nc a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 gnd nc nc sqw nc dq7 dq6 dq5 dq4 dq3 inta we ce oe intb (intb) 28pin encapsulated package (720 mil flush) pin description inta interrupt output a (open drain) intb (intb) interrupt output b (open drain) a0a5 address inputs dq0-dq7 data input/output ce chip enable oe output enable we write enable v cc +5 volts gnd ground nc no connection sqw square wave output description the DS1286 watchdog timekeeper is a selfcontained real time clock, alarm, watchdog timer, and interval tim- er in a 28pin jedec dip package. the DS1286 con- tains an embedded lithium energy source and a quartz crystal which eliminates the need for any external cir- cuitry. data contained within 64 eightbit registers can be read or written in the same manner as bytewide static ram. data is maintained in the watchdog timekeeper by intelligent control circuitry which detects the status of v cc and write protects memory when v cc is out of tol- erance. the lithium energy source can maintain data and real time for over ten years in the absence of v cc . watchdog timekeeper information includes hun- dredths of seconds, seconds, minutes, hours, day, date,
DS1286 022798 2/12 month, and year. the date at the end of the month is au- tomatically adjusted for months with less than 31 days, including correction for leap year. the watchdog time- keeper operates in either 24 hour or 12 hour format with an am/pm indicator. the watchdog timer provides alarm windows and interval timing between 0.01 sec- onds and 99.99 seconds. the real time alarm provides for preset times of up to one week. operation read registers the DS1286 executes a read cycle whenever we (write enable) is inactive (high) and ce (chip enable) and oe (output enable) are active (low). the unique address specified by the six address inputs (a0a5) de- fines which of the 64 registers is to be accessed. valid data will be available to the eight data output drivers within t acc (access time) after the last address input signal is stable, providing that ce and oe access times are also satisfied. if oe and ce access times are not satisfied, then data access must be measured from the latter occurring signal (ce or oe ) and the limiting pa- rameter is either t co for ce or t oe for oe rather than ad- dress access. operation write registers the DS1286 is in the write mode whenever the we (write enable) and ce (chip enable) signals are in the active (low) state after the address inputs are stable. the latter occurring falling edge of ce or we will deter- mine the start of the write cycle. the write cycle is termi- nated by the earlier rising edge of ce or we . all address inputs must be kept valid throughout the write cycle. we must return to the high state for a minimum recovery state (t wr ) before another cycle can be initiated. data must be valid on the data bus with sufficient data set up (t ds ) and data hold time (t dh ) with respect to the earlier rising edge of ce or we . the oe control signal should be kept inactive (high) during write cycles to avoid bus contention. however, if the output bus has been en- abled (ce and oe active), then we will disable the out- puts in t odw from its falling edge. data retention the watchdog timekeeper provides full functional ca- pability when v cc is greater than 4.5 volts and write pro- tects the register contents at 4.25 volts typical. data is maintained in the absence of v cc without any additional support circuitry. the DS1286 constantly monitors v cc . should the supply voltage decay, the watchdog time- keeper will automatically write protect itself and all in- puts to the registers become adon't careo. both inta and intb (intb) are open drain outputs. the two inter- rupts and the internal clock continue to run regardless of the level of v cc . however, it is important to insure that the pullup resistors used with the interrupt pins are never pulled up to a value which is greater than v cc + 0.3v. as v cc falls below approximately 3.0 volts, a power switching circuit turns the lithium energy source on to maintain the clock, and timer data functionality. it is also required to insure that during this time (battery backup mode), the voltage present at inta and intb (intb) does never exceed 3.0v. at all times the current on each should not exceed +2.1 ma or 1.0 ma. however, if the active high mode is selected for intb (intb), this pin will only go high in the presence of v cc . during powerup, when v cc rises above approxi- mately 3.0 volts, the power switching circuit connects external v cc and disconnects the internal lithium ener- gy source. normal operation can resume after v cc ex- ceeds 4.5 volts for a period of 150 ms. watchdog timekeeper registers the watchdog timekeeper has 64 registers which are eight bits wide that contain all of the timekeeping, alarm, watchdog, control, and data information. the clock, calendar, alarm, and watchdog registers are memory locations which contain external (useracces- sible) and internal copies of the data. the external co- pies are independent of internal functions except that they are updated periodically by the simultaneous trans- fer of the incremented internal copy (see figure 1). the command register bits are affected by both internal and external functions. this register will be discussed later. the 50 bytes of ram registers can only be ac- cessed from the external address and data bus. regis- ters 0, 1, 2, 4, 6, 8, 9, and a contain time of day and date information (see figure 2). time of day information is stored in bcd. registers 3, 5, and 7 contain the time of day alarm information. time of day alarm information is stored in bcd. register b is the command register and information in this register is binary. registers c and d are the watchdog alarm registers and informa- tion which is stored in these two registers is in bcd. registers e through 3f are user bytes and can be used to contain data at the user's discretion.
DS1286 022798 3/12 block diagram figure 1 command register update seconds thru years and check time of day alarm external registers, clock, calendar, time of day alarm user ram 50 bytes internal registers internal counters external registers watchdog alarm internal counters external registers hundredths of seconds divide by 4 swap pins power switch pf delay divide by 10 divide by 40.96 divide by 40.96 divide by 8 oscillator address decode adn countrol data i/0 buffers jitter generator oscillator & prescaler quartz crystal dq0-dq7 4096hz 32.768 lkz jitter generator (vbat) v cc 1024hz sqw (x1) (x2) 100hz 100hz aavgo a0-a5 ce oe we psur inta intb(intb) td int wd int aavgo internal registers
DS1286 022798 4/12 DS1286 watchdog timekeeper registers figure 2 0 1 2 3 4 5 6 7 8 9 a b c d e 3f address bit 7 bit 0 range 0.1 seconds 0.01 seconds 10 seconds seconds 10 minutes m min alarm 12/24 hr alarm days day alarm 10 date date 10mo months 10 years years te ipsw ibh lo pu lvl wam tdm waf tdf 0099 0059 0112+a/p 0023 0107 0131 0112 clock, calendar, time of day alarm registers command registers watchdog alarm registers user registers 0 0 minutes min alarm 10 a/p hours m m 12/24 10 a/p 00 00 0 0 00 0 0.1 seconds 0.01 seconds 10 seconds seconds 0 0 0059 0059 0099 0112+a/p 0023 0107 0099 0099 (retriggerable/ repetitive countdown alarm) 0 hr hr eosc esqw 0 10 10 10
DS1286 022798 5/12 time of day registers registers 0, 1, 2, 4, 6, 8, 9, and a contain time of day data in bcd. ten bits within these eight registers are not used and will always read zero regardless of how they are written. bits 6 and 7 in the months register (9) are binary bits. when set to logic zero, eosc (bit 7) enables the real time clock oscillator. this bit is set to logic one as shipped from dallas semiconductor to prevent lithium energy consumption during storage and shipment. this bit will normally be turned on by the user during device initialization. however, the oscillator can be turned on and off as necessary by setting this bit to the appropriate level. bit 6 of this same byte controls the square wave output (pin 23). when set to logic zero, the square wave output pin will output a 1024 hz square wave signal. when set to logic one the square wave output pin is in a high impedance state. bit 6 of the hours register is de- fined as the 12 or 24 hour select bit. when set to logic one, the 12hour format is selected. in the 12hour for- mat, bit 5 is the am/pm bit with logic one being pm. in the 24hour mode, bit 5 is the second 10hour bit (2023 hours). the time of day registers are updated every .01 seconds from the real time clock, except when the te bit (bit 7 of register b) is set low or the clock oscillator is not running. the preferred method of synchronizing data ac- cess to and from the watchdog timekeeper is to access the command register by doing a write cycle to address location 0b and setting the te bit (transfer enable ) to a logic zero. this will freeze the external time of day regis- ters at the present recorded time, allowing access to oc- cur without danger of simultaneous update. when the watch registers have been read or written, a second write cycle to location 0b, setting the te bit to a logic one, will put the time of day registers back to being updated every 0.01 second. no time is lost in the real time clock be- cause the internal copy of the time of day register buffers is continually incremented while the external memory registers are frozen. an alternate method of reading and writing the time of day registers is to ignore synchronization. however, any single read may give erroneous data as the real time clock may be in the process of updating the exter- nal memory registers as data is being read. the internal copies of seconds through years are incremented and time of day alarm is checked during the period that hundreds of seconds read 99 and are transferred to the external register when hundredths of seconds roll from 99 to 00. a way of making sure data is valid is to do mul- tiple reads and compare. writing the registers can also produce erroneous results for the same reasons. a way of making sure that the write cycle has caused proper update is to do read verifies and reexecute the write cycle if data is not correct. while the possibility of erro- neous results from reads and write cycles has been stated, it is worth noting that the probability of an incor- rect result is kept to a minimum due to the redundant structure of the watchdog timekeeper. time of day alarm registers registers 3, 5, and 7 contain the time of day alarm regis- ters. bits 3, 4, 5, and 6 of register 7 will always read zero regardless of how they are written. bit 7 of registers 3, 5, and 7 are mask bits (figure 3). when all of the mask bits are logic zero, a time of day alarm will only occur when registers 2, 4, and 6 match the values stored in regis- ters 3, 5, and 7. an alarm will be generated every day when bit 7 of register 7 is set to a logic one. similarly, an alarm is generated every hour when bit 7 of registers 7 and 5 is set to a logic 1. when bit 7 of registers 7, 5, and 3 is set to a logic 1, an alarm will occur every minute when register 1 (seconds) rolls from 59 to 00. time of day alarm registers are written and read in the same format as the time of day registers. the time of day alarm flag and interrupt is always cleared when alarm registers are read or written. watchdog alarm registers registers c and d contain the time for the watchdog alarm. the two registers contain a time count from 00.01 to 99.99 seconds in bcd. the value written into the watchdog alarm registers can be written or read in any order. any access to registers c or d will cause the watchdog alarm to reinitialize and clears the watchdog flag bit and the watchdog interrupt output. when a new value is entered or the watchdog registers are read, the watchdog timer will start counting down from the entered value to zero. when zero is reached, the watchdog interrupt output will go to the active state. the watchdog timer countdown is interrupted and rein- itialized back to the entered value every time either of the registers is accessed. in this manner, controlled pe- riodic accesses to the watchdog timer can prevent the watchdog alarm from ever going to an active level. if access does not occur, countdown alarm will be repeti- tive. the watchdog alarm registers always read the en- tered value. the actual countdown register is internal and is not readable. writing registers c and d to zero will disable the watchdog alarm feature.
DS1286 022798 6/12 command register address location 0b is the command register where mask bits, control bits, and flag bits reside. bit 0 is the time of day alarm flag (tdf). when this bit is set inter- nally to a logic one, an alarm has occurred. the time of the alarm can be determined by reading the time of day alarm registers. however, if the transfer enable bit is set to logic zero the time of day registers may not reflect the exact time that the alarm occurred. this bit is read only and writing this register has no effect on the bit. the bit is reset when any of the time of day alarm regis- ters are read. bit 1 is the watchdog alarm flag (waf). when this bit is set internally to a logic one, a watchdog alarm has occurred. this bit is read only and writing this register has no effect on the bit. the bit is reset when any of the watchdog alarm registers are accessed. bit 2 of the command register contains the time of day alarm mask bit (tdm). when this bit is written to a logic one, the time of day alarm interrupt output is deacti- vated regardless of the value of the time of day alarm flag. when tdm is set to logic zero, the time of day interrupt output will go to the active state which is deter- mined by bits 0, 4, 5, and 6 of the command register. bit 3 of the command register contains the watchdog alarm mask bit (wam). when this bit is written to a logic one, the watchdog interrupt output is deactivated re- gardless of the value in the watchdog alarm registers. when wam is set to logic zero, the watchdog interrupt output will go to the active state which is determined by bits 1, 4, 5, and 6 of the command register. these four bits define how interrupt output pins inta and intb (intb) will be operated. bit 4 of the command register determines whether both interrupts will output a pulse or level when activated. if bit 4 is set to logic one, the pulse mode is selected and inta will sink current for a mini- mum of 3 ms and then release. output intb (intb) will either sink or source current for a minimum of 3 ms de- pending on the level of bit 5. when bit 5 is set to logic one, the b interrupt will source current. when bit 5 is set to logic zero, the b interrupt will sink current. bit 6 of the command register directs which type of interrupt will be present on interrupt pins inta or intb (intb). when set to logic one, inta becomes the time of day alarm interrupt pin and intb (intb) becomes the watchdog interrupt pin. when bit 6 is set to logic zero, the interrupt functions are reversed such that the time of day alarm will be output on intb (intb) and the watchdog inter- rupt will be output on inta . caution should be exercised when dynamically setting this bit as the interrupts will be reversed even if in an active state. bit 7 of the command register is for transfer enable (te). the function of this bit is described in the time of day registers. time of day alarm mask bits figure 3 (3)minutes (5)hours (7)days 1 0 alarm once per minute alarm when minutes match alarm when hours and minutes match alarm when hours, minutes, and days match 11 1 1 1 0 0 00 0 register
DS1286 022798 7/12 absolute maximum ratings* voltage on any pin relative to ground 0.3v to +7.0v operating temperature 0 c to 70 c storage temperature 40 c to +70 c soldering temperature 260 c for 10 seconds (see note 14) * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0 c to 70 c) parameter symbol min typ max units notes supply voltage v cc 4.5 5.0 5.5 v 10 input logic 1 v ih 2.2 v cc + 0.3 v 10 input logic 0 v il 0.3 +0.8 v 10 dc electrical characteristics (0 c to 70 c; v cc = 5v + 10%) parameter symbol min typ max units notes input leakage current i il 1.0 +1.0 m a output leakage current i lo 1.0 +1.0 m a i/o leakage current i lio 1.0 +1.0 m a output current @ 2.4v i oh 1.0 ma output current @ 0.4v i ol 2.0 ma 13 standby current ce = 2.2v i ccs1 3.0 7.0 ma standby current ce > v cc 0.5 i ccs2 4.0 ma active current i cc 15 ma write protection voltage v tp 4.25 v capacitance (t a =25 c) parameter symbol min typ max units notes input capacitance c in 7 10 pf output capacitance c out 7 10 pf input/output capacitance c i/o 7 10 pf
DS1286 022798 8/12 ac electrical characteristics (0 c to 70 c; v cc = 4.5v to 5.5v) parameter symbol min typ max units notes read cycle time t rc 150 ns 1 address access time t acc 150 ns ce access time t co 150 ns oe access time t oe 60 ns oe or ce to output active t coe 10 ns output high z from deselect t od 60 ns output hold from address change t oh 10 ns write cycle time t wc 150 ns write pulse width t wp 140 ns 3 address setup time t aw 0 ns write recovery time t wr 10 ns output high z from we t odw 50 ns output active from we t oew 10 ns data setup time t ds 45 ns 4 data hold time t dh 0 ns 4,5 inta , intb pulse width t ipw 3 ms 11,12
DS1286 022798 9/12 read cycle (note1) addresses ce oe d out we addresses ce d out d in we addresses ce d out d in t rc v ih v il t od v oh v ol t aw t acc v ih v il v ih v il t oh t co v ih v ih t od v oh v ol t oe v ih t coe v il output data valid v ih t wc v il v ih t aw v il v ih v il v ih v il t wr t wp v ih v il v il t oew t odw high impedance t ds t dh v ih v il v ih v il data in stable t wc v il v ih t aw v ih v il v il t wp v il v ih v il v ih v ih t wr v il v ih v ih t odw t coe t ds t dh v ih v il v ih v il data in stable v il write cycle 1 (notes 2, 6, 7) write cycle 2 (notes 2, 8)
DS1286 022798 10/12 timing diagram: interrupt outputs pulse mode (see notes 11,12) intb inta , intb t ipw powerdown/powerup condition 3.2v data retention time 4.50v t dr t f t pd ce v cc t r t rec i l current, i l , supplied from lithium cell powerup/powerdown condition parameter symbol min typ max units notes ce at v ih before power-down t pd 0 m s v cc slew from 4.5v to 0v (ce at v ih ) t f 350 m s v cc slew from 0v to 4.5v (ce at v ih ) t r 100 m s ce at v ih after power up t rec 150 ms (t a =25 c) parameter symbol min typ max units notes expected data retention time t dr 10 years 9 warning: under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery backup mode.
DS1286 022798 11/12 notes: 1. we is high for a read cycle. 2. oe = v ih or v il . if oe = v ih during write cycle, the output buffers remain in a high impedance state. 3. t wp is specified as the logical and of the ce and we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4. t ds or t dh are measured from the earlier of ce or we going high. 5. t dh is measured from we going high. if ce is used to terminate the write cycle, then t dh = 20 ns. 6. if the ce low transition occurs simultaneously with or later than the we low transition in write cycle 1, the output buffers remain in a high impedance state during this period. 7. if the ce high transition occurs prior to or simultaneously with the we high transition, the output buffers remain in a high impedance state during this period. 8. if we is low or the we low transition occurs prior to or simultaneously with the ce low transition, the output buffers remain in a high impedance state during this period. 9. each DS1286 is marked with a four digit date code aabb. aa designates the year of manufacture. bb designates the week of manufacture. the expected t dr is defined as starting at the date of manufacture. 10. all voltages are referenced to ground. 11. applies to both interrupt pins when the alarms are set to pulse. 12. interrupt output occurs within 100 ns on the alarm condition existing. 13. both inta and intb (intb) are open drain outputs. 14. realtime clock modules can be successfully processed through conventional wavesoldering techniques as long as temperature exposure to the lithium energy source contained within does not exceed +85 c. post solder cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used. ac test conditions output load: 100 pf + 1ttl gate input pulse levels: 03.0v timing measurement reference levels input: 1.5v output: 1.5v input pulse rise and fall times: 5 ns.
DS1286 022798 12/12 DS1286 watchdog timekeeper a 28 114 15 c e f k d g b h j dim min max a in. mm b in. mm c in. mm d in. mm e in. mm f in. mm g in. mm h in. mm j in. mm k in. mm 1.520 38.61 1.540 39.12 0.695 17.65 0.720 18.29 0.350 8.89 0.375 9.52 0.100 2.54 0.130 3.30 0.015 0.38 0.030 0.76 0.110 2.79 0.140 3.56 0.090 2.29 0.110 2.79 0.590 14.99 0.630 16.00 0.008 0.20 0.012 0.30 0.015 0.38 0.021 0.53 28pin pkg 13 equal spaces at .100 .010 tna note: pins 2, 3, 21, 24 and 25 are missing by design.

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